The present invention concerns the reduction of simultaneous switching noise in output circuitry on an integrated circuit.
In integrated circuits which are tested using a boundary scan test strategy, a serial shift register, also called a boundary scan register, is included for use in board level testing. The serial shift register allows that, with a reduced pin count, a test pattern can be loaded into the serial shift register and applied to the chip output pins during board level testing.
Generally, it is required that during the loading of the serial shift register, the values within the serial shift register not be reflected until after the loading of the serial register is complete. For this reason an additional output holding register is connected between the serial shift register and the output pins. This conforms with the Joint Test Action Group (JTAG) IEEE P1149 standard.
When a test pattern within the serial shift register is loaded into the output holding register, and subsequently driven onto the chip output pins, there exists a good possibility that many more output pins will be switching simultaneously than in the normal functional mode. This is because the testing is not constrained to system functional limitations, because all bit slices of the output holding register are uniform in design and hence each bit of output has a similar propagation delay, and because each test vector exercises as much as possible in order to reduce testing time and hence the cost of testing.
The level of simultaneous switching that occurs during testing can cause a larger amount of simultaneous switching output noise than occurs during normal operation. This excess simultaneous switching output noise can result in a degradation of performance of the integrated circuit during testing.
One way to overcome degradation of integrated circuit performance during testing because of increased simultaneous switching output noise is to design the integrated circuit so that sufficient current is available to reduce the simultaneous switching output noise. This, however, can greatly add to the expensive of the integrated circuit. Another way to overcome the degradation during testing is to limit the switching during the test by either blocking the test structures into groups and exercising them separately, or by writing the test patterns in such a way as to avoid excessive simultaneous switching output. This approach, however, limits the ability to observe test data and control testing and thus thwarts the goal of using boundary scan registers to eliminate such limitations.